CASIA OpenIR
(本次检索基于用户作品认领结果)

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Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips 会议论文
, Beijing,China, 2018,11.23-25
作者:  Hongyu,Meng;  Yang,Guo;  Zijun.Liu;  Donglin.Wang
浏览  |  Adobe PDF(345Kb)  |  收藏  |  浏览/下载:294/96  |  提交时间:2019/05/06
Task Scheduling  Multi-core  Shared Memory  Traffic-aware  Memory-aware  
A Design Space Exploration Method for on-Chip Memory System Based on Task Scheduling 会议论文
, Beijing,China, 2018,11.23-25
作者:  Hongyu,Meng;  Pengfei.Ding;  Mingxuan.Wang;  Donglin.Wang
浏览  |  Adobe PDF(288Kb)  |  收藏  |  浏览/下载:284/100  |  提交时间:2019/05/06
Design Space Exploration  Multi-core Architecture  Memory System  Task Scheduling  
Low Latency Spiking ConvNets with Restricted Output Training and False Spike Inhibition 会议论文
, 巴西里约热内卢, 2018-7
作者:  Chen RZ(陈睿智);  Ma H(马鸿);  Guo P(郭鹏);  Xie SL(谢少林);  Wang DL(王东琳)
浏览  |  Adobe PDF(11839Kb)  |  收藏  |  浏览/下载:247/83  |  提交时间:2019/05/06
Fast and Efficient Deep Sparse Multi-Strength Spiking Neural Networks with Dynamic Pruning 会议论文
, 巴西里约热内卢, 2018-7
作者:  Chen RZ(陈睿智);  Ma H(马鸿);  Xie SL(谢少林);  Guo P(郭鹏);  Li P(李品);  Wang DL(王东琳)
浏览  |  Adobe PDF(5380Kb)  |  收藏  |  浏览/下载:277/102  |  提交时间:2019/05/06
FBNA: A Fully Binarized Neural Network Accelerator 会议论文
, 爱尔兰都柏林, 2018-8
作者:  Guo Peng;  Hong Ma;  Ruizhi Chen;  Pin Li;  Shaolin Xie;  Donglin Wang
浏览  |  Adobe PDF(824Kb)  |  收藏  |  浏览/下载:370/141  |  提交时间:2019/06/17
Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on Chip 会议论文
, Beijing,China, 2018,6.15-17
作者:  Hongyu,Meng;  Donglin,Wang;  Zijun,Liu;  Yang,Guo
浏览  |  Adobe PDF(318Kb)  |  收藏  |  浏览/下载:306/104  |  提交时间:2019/05/06
Interconnect  Crossbar  Multi-cores  Shared-memory  
A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration 会议论文
, 中国科技会堂, 2017-11
作者:  Feng Jing;  Zijun Liu;  Xiaojun Ma;  Guo Yang;  Guo Peng;  Donglin Wang
浏览  |  Adobe PDF(576Kb)  |  收藏  |  浏览/下载:505/199  |  提交时间:2018/05/31
Compression  High Speed  Multi-granularity  Parallel  Power Efficient  Reuse  Reconfigurable  
An automatic and practical flow for clock tree construction in physical design 会议论文
, Beijing, 26-28 Aug. 2016
作者:  Meng Liu;  Wenqin Sun;  Wuqi Wang;  Zhiwei Zhang;  Donglin Wang
Adobe PDF(825Kb)  |  收藏  |  浏览/下载:466/199  |  提交时间:2017/10/09
Optimal Many-to-Many Personalized Concurrent Communication in RapidIO-based Fat-trees 会议论文
17th IEEE/ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing (SNPD 2016), Shanghai,China, 2016.05.30-2016.06.01
作者:  Shu Lin;  Hao,Jie;  Song,Yafang;  Li,Chengcheng;  Wang,Donglin;  Shu,Lin
浏览  |  Adobe PDF(775Kb)  |  收藏  |  浏览/下载:366/60  |  提交时间:2016/06/27
Many-to-many  Personalized  Rapidio  Fat-tree  Node-level  Congestion-avoidance  
Parallel Implementation of Arbitrary-Sized Discrete Fourier Transform on FPGA 会议论文
2016 3rd International Conference on Advanced Computing and Communication Systems (ICACCS -2016), Coimbatore, INDIA, 2016.01.22-2016.01.23
作者:  Shu Lin;  Hao,Jie;  Li,Chengcheng;  Feng,Hui;  Wang,Donglin;  Shu,Lin
浏览  |  Adobe PDF(368Kb)  |  收藏  |  浏览/下载:348/87  |  提交时间:2016/06/27
Dft  Arbitrary-sized  Parallel  Fpga