CASIA OpenIR

浏览/检索结果: 共6条,第1-6条 帮助

限定条件    
已选(0)清除 条数/页:   排序方式:
Traffic-Aware and Memory-Aware Task Scheduling on Multi-Core Chips 会议论文
, Beijing,China, 2018,11.23-25
作者:  Hongyu,Meng;  Yang,Guo;  Zijun.Liu;  Donglin.Wang
浏览  |  Adobe PDF(345Kb)  |  收藏  |  浏览/下载:291/96  |  提交时间:2019/05/06
Task Scheduling  Multi-core  Shared Memory  Traffic-aware  Memory-aware  
A Distributed Register File Architecture Based on Dynamic Scheduling for VLIW Machine 会议论文
, 北京, 2018-6
作者:  Yang Guo;  Donglin Wang;  Zijun Liu;  Hongyu Meng
浏览  |  Adobe PDF(203Kb)  |  收藏  |  浏览/下载:299/122  |  提交时间:2019/05/10
Parallel Polar Encoding in 5G Communication 会议论文
, 巴西纳塔尔, 2018-6
作者:  Yang Guo;  Shaolin Xie;  Zijun Liu;  Lei Yang;  Donglin Wang
浏览  |  Adobe PDF(377Kb)  |  收藏  |  浏览/下载:330/113  |  提交时间:2019/05/10
Advanced Extensible Crossbar Protocol for Connecting Multi-Cores and Shared-Memory on Chip 会议论文
, Beijing,China, 2018,6.15-17
作者:  Hongyu,Meng;  Donglin,Wang;  Zijun,Liu;  Yang,Guo
浏览  |  Adobe PDF(318Kb)  |  收藏  |  浏览/下载:302/103  |  提交时间:2019/05/06
Interconnect  Crossbar  Multi-cores  Shared-memory  
Progress in a novel architecture for high performance processing 期刊论文
JAPANESE JOURNAL OF APPLIED PHYSICS, 2018, 卷号: 57, 期号: 4
作者:  Zhang, Zhiwei;  Liu, Meng;  Liu, Zijun;  Du, Xueliang;  Xie, Shaolin;  Ma, Hong;  Ding, Guangxin;  Ren, Weili;  Zhou, Fabiao;  Sun, Wenqin;  Wang, Huijuan;  Wang, Donglin
收藏  |  浏览/下载:293/0  |  提交时间:2018/10/10
A reconfigurable high-performance multiplier based on multi-granularity design and parallel acceleration 会议论文
, 中国科技会堂, 2017-11
作者:  Feng Jing;  Zijun Liu;  Xiaojun Ma;  Guo Yang;  Guo Peng;  Donglin Wang
浏览  |  Adobe PDF(576Kb)  |  收藏  |  浏览/下载:498/196  |  提交时间:2018/05/31
Compression  High Speed  Multi-granularity  Parallel  Power Efficient  Reuse  Reconfigurable